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general description the MAX17007A/max17008 are dual quick-pwm? step-down controllers intended for general power gen- eration in battery-powered systems. the two switched- mode power supplies (smpss) can also be combined to operate in a two-phase single-output mode. constant on-time quick-pwm operation provides fast response to load transients and handles wide input/output (i/o) volt- age ratios with ease, while maintaining a relatively con- stant switching frequency. the switching frequency can be individually adjusted between 200khz and 600khz with external resistors. differential output current sens- ing allows output sense-resistor sensing for an accurate current limit, or lossless inductor direct-current resis- tance (dcr) current sensing for lower power dissipation while maintaining 0.7% output accuracy. overvoltage (MAX17007A only), undervoltage protection, and accu- rate user-selectable current limits (15mv, 30mv, 45mv, and 60mv) ensure robust operations. the smps outputs can operate in skip mode or in ultra- sonic mode for improved light-load efficiency. the ultra- sonic mode eliminates audible noises by maintaining a minimum switching frequency of 25khz in pulse- skipping mode. the output voltage of smps1 can be dynamically adjusted by changing the voltage at the refin1 pin. the device includes a 0.5% accurate reference output that can be used to set the refin1 voltage. an external 5v bias supply is required to power the internal circuitry and its gate drivers. independent on/off controls with well-defined logic thresh- olds and independent open-drain power-good outputs provide flexible system configurations. to prevent current surges at startup, the internal voltage target is slowly ramped up from zero to the final target with a slew rate of 1.3mv/s for smps1 at csl1 and 0.65mv/s for smps2 at fb2. to prevent the output from ringing off below ground in shutdown, the internal voltage target is ramped down from its previous value to zero with the same respective slew rates. integrated bootstrap switches eliminate the need for external bootstrap diodes. the MAX17007A/max17008 are available in a space- saving, 28-pin, 4mm x 4mm, thin qfn package with an exposed backside pad. applications features dual quick-pwm with fast transient response automatic dynamic refin1 detection and pgood1/fault blanking fixed and adjustable output voltages ?.7% output accuracy over line and load out1: 0 to 2v dynamic output or preset 1.05v out2: 0.7v to 2v range or preset 1.5v resistor-programmable switching frequency integrated bst switches differential current-sense inputs low-cost dcr sensing or accurate current- sense resistors internally coupled current-sense compensation combinable mode supports high-current dynamic output voltages selectable forced-pwm, pulse skip, or ultrasonic mode operation 26v maximum input voltage rating independent enable inputs independent power-good outputs overvoltage protection (MAX17007A only) undervoltage/thermal protection voltage soft-start and soft-shutdown MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ________________________________________________________________ maxim integrated products 1 MAX17007A max17008 18 thin qfn (4mm x 4mm) 4 17 5 16 6 15 14 22 7 19 3 20 2 21 13 23 12 24 11 25 10 26 9 27 8 28 1 lx1 dh1 pgood1 en1 csh1 top view *ep *ep = exposed pad. csl1 refin1 lx2 dh2 pgood2 en2 csh2 csl2 fb2 bst2 pgnd dl2 v dd dl1 gnd bst1 ref ilim1 (cci) ilim2 v cc skip ton1 ton2 + pin configuration ordering information 19-3200; rev 2; 10/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17007A gti+ -40c to +105c 28 thin qfn-ep* max17008 gti+ -40c to +105c 28 thin qfn-ep* notebook computers low-power i/o supplies gpu core supplies 2 to 4 li+ cells battery- powered devices quick-pwm is a trademark of maxim integrated products, inc.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = 0 to +85?, unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. bst1, bst2 to gnd ...............................................-0.3v to +34v bst1, bst2 to v dd .................................................-0.3v to +28v ton1, ton2 to gnd..............................................-0.3v to +28v v dd to gnd ..............................................................-0.3v to +6v v dd to v cc ............................................................-0.3v to +0.3v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) ilim1, ilim2, ref to gnd ..........................-0.3v to (v cc + 0.3v) csh1, csh2, csl1, csl2, fb2, refin1 to gnd....-0.3v to +6v en1, en2, skip , pgood1, pgood2 to gnd.........-0.3v to +6v dl1 to gnd ................................................-0.3v to (v dd + 0.3v) dl2 to pgnd..............................................-0.3v to (v dd + 0.3v) pgnd to gnd ......................................................-0.3v to + 0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70c) 28-pin tqfn t2844-1 (derate 20.8mw/c above +70c) ............................1667mw extended operating temperature range .........-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller input voltage range v in 4.5 26 v quiescent supply current (v dd , v cc ) i dd + i cc output forced above regulation voltage, v en1 = v en2 = 5v 1.7 2.5 ma shutdown supply current (v dd , v cc ) i shdn en1 = en2 = gnd, t a = +25c 0.1 5 a r ton1 = r ton2 = 97.5k (600khz) 142 (-15%) 174 194 (+15%) r ton1 = r ton2 = 200k (300khz) 305 (-10%) 336 368 (+10%) on-time (note 1) t on1 , t on2 v in = 12v, v csl1 = v csl2 = v cci = 1.2v, separate or combined mode r ton1 = r ton2 = 302.5k (200khz) 425 (-15%) 500 575 (+15%) ns minimum off-time t off(min) (note 1) 250 400 ns ton1, ton2, shutdown supply current i ton1 , i ton2 en1 = en2 = gnd, v ton1 = v ton2 = 26v, v dd = 0 or 5v, t a = +25c 0.01 1 a refin1 voltage range v refin1 (note 2) 0 v ref v fb2 regulation voltage v fb2 adjustable mode 0.7 v fb2 input voltage range preset mode 1.7 2.3 v fb2 combined-mode threshold combined mode 3.8 v cc - 1v v cc - 0.4 v refin1 dual mode? switchover threshold 3.8 v cc - 1v v cc - 0.4 v refin1, fb2 bias current i refin1 , i fb2 refin1 = 0.5v to 2v; v fb2 = 0.7v, t a = +25c -0.1 +0.1 a v csl1 measured at csl1, refin1 = v cc , v in = 2v to 26v, skip = v cc (note 2) 1.043 1.05 1.057 v t a = +25c -12 +12 refin1 = 500mv, skip = v cc t a = 0c to +85c -20 +20 smps1 voltage accuracy v csl1 - v refin1 refin1 = 2v, skip = v cc -20 +20 mv dual mode is a trademark of maxim integrated products, inc.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units smps2 voltage accuracy v csl2 measured at csl2, fb2 = ref, v in = 2v to 26v, skip = v cc 1.489 1.5 1.511 v load regulation error i load = 0 to full load, skip = v cc (note 3) 0.1 % line regulation error v dd = 4.5v to 5.5v, v in = 4.5v to 26v (note 3) 0.25 % csl1 soft-start/-stop slew rate sr ss1 rising/falling edge on en1 1.25 mv/s fb2 soft-start/-stop slew rate sr ss2 rising/falling edge on en2 0.63 mv/s dynamic refin1 slew rate sr dyn rising edge on refin1 11.4 mv/s internal reference reference voltage v ref v dd = 4.5v to 5.5v 1.990 2.000 2.010 v reference lockout voltage v ref(uvlo) rising edge, hysteresis = 230mv 1.8 v reference load regulation i ref = -10a to +100a 1.980 2.015 mv fault detection with respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mv 260 300 340 mv dynamic transition v ref + 0.30 v smps1 overvoltage trip threshold and pgood1 upper threshold (MAX17007A only) v ovp1 , v pg1_h minimum ovp threshold 0.7 v smps2 adjustable mode overvoltage trip threshold and pgood2 upper threshold (MAX17007A only) v ovp2 , v pg2_h with respect to the internal target voltage 0.7v (error comparator threshold); hysteresis = 50mv 120 150 180 mv output overvoltage fault propagation dela y (MAX17007A only) t ovp csl1/fb2 forced 25mv above trip threshold 5 s smps1 undervoltage protection trip threshold and lower pgood1 threshold v uvp1 , v pg1_l with respect to the internal target voltage (error comparator threshold); falling edge; hysteresis = 50mv -240 -200 -160 mv smps2 undervoltage protection trip threshold and lower pgood2 threshold v uvp2 , v pg2_l with respect to the internal target voltage 0.7v (error comparator threshold); falling edge; hysteresis = 50mv -130 -100 -70 mv output undervoltage fault propagation dela y t uvp csl1/fb2 forced 25mv below trip threshold 90 205 360 s uvp falling edge, 25mv overdrive 5 ovp rising edge, 25mv overdrive 5 pgood_ propagation delay t pgood startup delay from regulation 90 205 360 s pgood_ output low voltage i sink = 3ma 0.4 v pgood_ leakage current i pgood csl1 = refin1, fb2 = 0.7v (pgood_ high impedance), pgood_ forced to 5v, t a = +25c 1 a dynamic refin1 transition fault-blanking threshold fault blanking initiated; refin1 deviation from the internal target voltage (error comparator threshold); hysteresis = 10mv 50 mv thermal-shutdown threshold t shdn hysteresis = 15c (note 3) 160 c v cc undervoltage lockout threshold v uvlo(vcc) rising edge, pwm disabled below this level, hysteresis = 100mv 3.95 4.20 4.45 v electrical characteristics (continued) (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = 0 to +85?, unless otherwise noted. typical values are at t a = +25c.)
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = 0 to +85?, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units current limit csh1, csh2 0 2.3 current-sense input range csl1, csl2 0 2.3 v current-sense input (csh_) leakage current csh_ = gnd or v cc , t a = +25c -0.2 +0.2 a current-sense input (csl_) leakage current csl_= csl_ = 2v, t a = +25c 1 a t a = +25c 28 30 32 v csh_ - v csl_ ilim1 = ilim2 = ref t a = 0c to +85c 27 30 33 v csh_ - v csl_ , ilim1 = ilim2 = v cc 56 60 64 v csh_ - v csl_ , ilim1 = ilim2 = open 42 45 48 current-limit threshold (fixed) v cslimit v csh_ - v csl_, ilim1 = ilim2 = gnd 13 15 17 mv current-limit threshold (negative) v neg v csh_ - v csl_ , skip = v cc -1.2 x v cslimit mv current-limit threshold (zero crossing) v zx v csh_ - v csl_ , skip = gnd or open; ilim1 = ilim2 = ref 1 mv ultrasonic frequency skip = open (3.3v); v csl1 = v refin1 + 50mv; v csl2 = v fb2 + 50mv 20 khz v csl1 = v ref1 + 50mv 22 33 46 ultrasonic current-limit threshold skip = open (3.3v) v csl2 = v fb2 + 50mv 18 30 46 mv current-balance amplifier (gmi) offset [v(csh1,csl1) - v(csh2,csl2)] at i cci = 0 -3 +3 mv current-balance amplifier (gmi) transconductance i cci / [v(csh1,csl1) - v(csh2,csl2)]; v cci = v csl1 = v csl2 = 0.5v to 2v, and v(csh_,csl_) = -60.0mv to +60.0mv, ilim1 = gnd 180 s gate drivers low state (pulldown) 1.7 4.0 dh1, dh2 gate-driver on-resistance r on(dh) bst_ - lx_ forced to 5v high state (pullup) 1.7 4.0 high state (pullup) 1.3 3.0 dl1, dl2 gate-driver on-resistance r on(dl) low state (pulldown) 0.6 2.5 dh1, dh2 gate-driver source/sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 1.2 a dl1, dl2 gate-driver source current i dl(source) dl_ forced to 2.5v 1 a dl1, dl2 gate-driver sink current i dl(sink) dl_ forced to 2.5v 2.4 a dh_ low to dl high 10 25 40 driver propagation delay dl_ low to dh high 15 30 45 ns
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = 0 to +85?, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units dl_ falling, c dl = 3nf 10 20 dl_ transition time dl_ rising, c dl = 3nf 10 20 ns dh_ falling, c dh = 3nf 10 20 dh_ transition time dh_ rising, c dh = 3nf 10 20 ns internal bst_ switch on-resistance r bst_ i bst_ = 10ma, v dd = 5v 6.5 11.0 inputs and outputs en1, en2 logic-input threshold en1, en2 rising edge, hysteresis = 300mv/600mv (min/max) 1.20 1.70 2.20 v logic-input current en1, en2, t a = +25c -0.5 +0.5 a high (5v) v cc - 0.3 open (3.3v) 3.0 3.6 ref (2.0v) 1.7 2.3 quad-level input-logic levels skip , ilim1, ilim2 low (gnd) 0.4 v quad-level logic-input current skip , ilim1, ilim2 forced to gnd or v cc , t a = +25c -2 +2 a electrical characteristics (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min max units pwm controller input voltage range v in 4.5 26 v quiescent supply current (v dd , v cc ) i dd + i cc output forced above regulation voltage, v en1 = v en2 = 5v 2.5 ma r ton1 = r ton2 = 97.5k (600khz) 142 194 r ton1 = r ton2 = 200k (300khz) 305 368 on-time (note 1) t on1 , t on2 v in = 12v, v csl1 = v csl2 = v cci = 1.2v, separate or combined mode r ton1 = r ton2 = 302.5k (200khz) 425 575 ns minimum off-time t off(min) (note 1) 400 ns refin1 voltage range v refin1 0 v ref v fb2 input voltage range preset mode 1.7 2.3 v fb2 combined-mode threshold combined mode 3.75 v cc - 0.4 v refin1, fb2 bias current i refin1 , i fb2 -0.1 +0.1 a
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min max units refin1 dual-mode switchover threshold 3.75 v cc - 0.4 v smps1 voltage accuracy v csl1 measured at csl1, refin1 = v cc; v in = 2v to 26v, skip = v cc (note 2) 1.039 1.061 v smps2 voltage accuracy v csl2 measured at csl2, fb2 = ref; v in = 2v to 26v, skip = v cc (note 2) 1.485 1.515 v internal reference reference voltage v ref v dd = 4.5v to 5.5v 1.985 2.015 v fault detection smps1 overvoltage trip threshold and pgood1 upper threshold (MAX17007A only) v ovp1 , v pg1_h with respect to the internal target voltage (error comparator threshold); rising edge; hysteresis = 50mv 260 340 mv smps2 overvoltage trip threshold and pgood2 upper threshold (MAX17007A only) v ovp2 , v pg2_h with respect to the internal target voltage 0.7v (error comparator threshold); hysteresis = 50mv 120 180 mv smps1 undervoltage protection trip threshold and lower pgood1 threshold v uvp1 , v pg1_l with respect to the internal target voltage (error comparator threshold) falling edge; hysteresis = 50mv -240 -160 mv smps2 undervoltage protection trip threshold and lower pgood2 threshold v uvp2 , v pg2_l with respect to the internal target voltage 0.7v (error comparator threshold) falling edge; hysteresis = 50mv -130 -70 mv output undervoltage fault propagation dela y t uvp refin1/fb2 forced 25mv below trip threshold 90 360 s pgood_ propagation delay t pgood startup delay from regulation 90 360 s pgood_ output low voltage i sink = 3ma 0.4 v v cc undervoltage lockout threshold v uvlo(vcc) rising edge, pwm disabled below this level; hysteresis = 100mv 3.8 4.45 v current limit csh1, csh2 0 2.3 current-sense input range csl1, csl2 0 2.3 v current-limit threshold (fixed) v cslimit v csh_ - v csl_ , ilim1 = ilim2 = ref 27 33 mv ultrasonic frequency skip = open (3.3v); v csl1 = v refin1 + 50mv; v csl2 = v fb2 + 50mv 18 khz v csl1 = v ref1 + 50mv 22 46 ultrasonic current-limit threshold skip = open (3.3v) v csl2 = v fb2 + 50mv 18 46 mv current-balance amplifier (gmi) offset [v(csh1,csl1) - v(csh2,csl2)] at i cci = 0 -3 +3 mv
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers _______________________________________________________________________________________ 7 note 1: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = gnd, v bst = 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times might differ due to mosfet switching speeds. note 2: the 0 to 0.5v range is guaranteed by design, not production tested. note 3: not production tested. note 4: specifications at t a = -40c to +105c are guaranteed by design, not production tested. electrical characteristics (continued) (v in = 12v, v dd = v cc = v en1 = v en2 = 5v, v refin1 = 2v, skip = gnd, t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min max units gate drivers low state (pulldown) 4.5 dh1, dh2 gate-driver on-resistance r on(dh) bst_ - lx_ forced to 5v high state (pullup) 4.0 high state (pullup) 3 dl1, dl2 gate-driver on-resistance r on(dl) low state (pulldown) 2.5 dh_ low to dl high 8 42 driver propagation delay dl_ low to dh high 12 48 ns internal bst_ switch on-resistance r bst_ i bst_ = 10ma, v dd = 5v 12 inputs and outputs en1, en2 logic-input threshold en1, en2 rising edge; hysteresis = 300mv/600mv (min/max) 1.20 2.20 v high (5v) v cc - 0.3 open (3.3v) 3.0 3.6 ref (2.0v) 1.7 2.3 quad-level input logic levels skip , ilim1, ilim2 low (gnd) 0.4 v
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 8 _______________________________________________________________________________________ typical operating characteristics (circuit of figure 1, v in = 12v, v dd = 5v, skip = gnd, t a = +25c, unless otherwise noted.) smps2 1.5v efficiency vs. load current MAX17007A/8 toc01 load current (a) efficiency (%) 10 1 0.1 50 60 70 80 90 100 40 20 30 10 0.01 100 6v 12v 20v skip mode pwm mode smps2 1.5v efficiency vs. load current MAX17007A/8 toc02 load current (a) efficiency (%) 10 1 0.1 50 60 70 80 90 100 40 20 30 10 0.01 100 skip mode pwm mode v in = 12v ultrasonic mode smps2 1.5v output voltage vs. load current MAX17007A/8 toc03 load current (a) output voltage (v) 10 5 1.50 1.52 1.54 1.48 015 skip mode ultrasonic mode pwm v in = 12v combined 1.2v efficiency vs. load current MAX17007A/8 toc04 load current (a) efficiency (%) 10 1 0.1 50 60 70 80 90 100 40 20 30 10 0.01 100 skip mode pwm mode 6v 12v 20v combined 1.2v output voltage vs. load current MAX17007A/8 toc05 load current (a) output voltage (v) 16 20 8 424 12 1.19 1.20 1.21 1.22 1.18 028 skip mode pwm v in = 12v smps2 switching frequency vs. load current MAX17007A/8 toc06 load current (a) switching frequency (khz) 10 1 0.1 200 250 300 350 150 50 100 0 0.01 100 skip mode pwm mode v in = 12v ultrasonic mode smps2 switching frequency vs. input voltage MAX17007A/8 toc07 input voltage (v) switching frequency (khz) 20 424 250 300 350 200 028 81216 v in = 12v skip = 5v i out2 = 5a i out2 = 0a smps2 switching frequency vs. temperature MAX17007A/8 toc08 temperature ( c) switching frequency (khz) 040 -20 60 290 270 310 330 250 -40 120 100 80 20 v in = 12v skip = 5v i out2 = 5a i out2 = 0a smps2 maximum output current vs. input voltage MAX17007A/8 toc09 input voltage (v) maximum output current (a) 20 424 12 11 13 14 10 028 81216
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers _______________________________________________________________________________________ 9 smps2 maximum output current vs. temperature MAX17007A/8 toc10 temperature ( c) maximum output current (a) 80 40 0 11 12 13 14 10 -40 120 60 20 -20 100 v in = 12v no-load supply current vs. input voltage MAX17007A/8 toc11 input voltage (v) supply currert (i bias ) (ma) 20 16 4 8 12 16 0 6 10 14 2 424 812 skip mode pwm mode ultrasonic mode en1 = high en2 = low no-load input current vs. input voltage MAX17007A/8 toc12 input voltage (v) input current (ma) 20 16 0.1 1 10 100 0.01 424 812 18 14 22 610 skip mode pwm mode ultrasonic mode en1 = high en2 = low reference voltage vs. reference load current MAX17007A/8 toc13 reference load current ( a) reference voltage (v) 80 60 1.99 1.97 2.01 2.03 2.05 1.95 -20 100 20 40 0 refin1 to csl1 offset voltage distribution MAX17007A/8 toc14 offset voltage (mv) sample percentage (%) 3.0 60 50 70 80 20 10 30 40 90 0 -5.0 5.0 -1.0 1.0 -3.0 sample size = 100 t a = +85 c t a = +25 c smps1 preset 1.05v voltage distribution MAX17007A/8 toc15 smps1 voltage (mv) sample percentage (%) 1.053 60 50 70 80 20 10 30 40 90 0 1.045 1.055 1.049 1.051 1.047 sample size = 100 t a = +85 c t a = +25 c smps2 preset 1.5v voltage distribution MAX17007A/8 toc16 smps2 voltage (mv) sample percentage (%) 1.503 15 10 20 25 5 30 0 1.495 1.505 1.499 1.501 1.497 sample size = 100 t a = +85 c t a = +25 c combined-mode current balance vs. load current MAX17007A/8 toc17 load current (a) v csh - v csl (mv) 20 15 525 10 50 40 20 10 30 0 030 smps1 smps2 soft-start waveform MAX17007A/8 toc18 400 s/div a b e f c d 5v a. en1, en2, 5v/div b. ref, 2v/div c. v out1 , 1v/div d. v out2 , 1v/div e. pgood1, 5v/div f. pgood2, 5v/div 0 2v 0 5v 0 0 5v 0 1.05v 1.5v 0 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = 5v, skip = gnd, t a = +25c, unless otherwise noted.)
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 10 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = 5v, skip = gnd, t a = +25c, unless otherwise noted.) smps1 startup waveform (heavy load) MAX17007A/8 toc19 200 s/div a b e f g c d 5v a. en1, 5v/div b. ref, 2v/div c. v out1 , 500mv/div d. i lx1 , 10a/div e. pgood1, 10v/div f. lx1, 10v/div g. dl1, 10v/div 0 2v 5v 0 12v 0 5v 0 0 1.05v 0 8a i out1 = 8a smps1 startup waveform (light load) MAX17007A/8 toc20 200 s/div a b e f g c d 5v a. en1, 5v/div b. ref, 2v/div c. v out1 , 500mv/div d. i lx1 , 5a/div skip = 5v i out1 = 2a e. pgood1, 10v/div f. lx1, 10v/div g. dl1, 10v/div 0 2v 0 1.05v 0 2a 0 5v 0 5v 0 0 12v smps1 shutdown waveform MAX17007A/8 toc21 200 s/div a b e f g c d 5v a. en1, 5v/div b. ref, 5v/div c. v out1 , 500mv/div d. i lx1 , 5a/div e. pgood1, 10v/div f. lx1, 10v/div g. dl1, 10v/div i out1 = 0.5a skip = gnd 0 2v 1.05v 0 0 0 5v 0 5v 0 12v smps2 load-transient response (pwm mode) MAX17007A/8 toc22 20 s/div a b c a. v out2 , 50mv/div b. i lx2 , 10a/div c. lx2, 10v/div 1.5v 10a 2a 12v 0 i out2 = 2a to 10a to 2a skip = 5v smps2 load-transient response (skip mode) MAX17007A/8 toc23 20 s/div a b c a. v out2 , 50mv/div b. i lx2 , 10a/div c. lx2, 10v/div 1.5v 8a 0a 12v 0 i out2 = 0.5a to 8.5a to 0.5a skip = gnd smps1 output overload waveform MAX17007A/8 toc24 200 s/div a b e c d i out1 = 2a to 15a a. v out1 , 500mv/div b. i lx1 , 10a/div c. lx1, 10v/div 1.05v 10a 2a 5v 0 5v 12v 0 0 d. pgood1, 5v/div e. dl1, 5v/div smps1 output overvoltage waveform MAX17007A/8 toc25 40 s/div a b c a. v out1 , 1v/div b. pgood1, 5v/div c. dl1, 5v/div 1.05v 0 5v 0 5v 0
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 11 dynamic output voltage transition (pwm mode) MAX17007A/8 toc26 20 s/div a b c d i out1 = 2a refin1 = 1v to 1.2v to 1v 1.2v 1v 0 2a 12v 0 5v a. v out1 , 100mv/div b. i lx1 , 10a/div c. lx1, 10v/div d. dl1, 5v/div skip = 5v dynamic output voltage transition (skip mode) MAX17007A/8 toc27 40 s/div a b c d i out1 = 1a 1.2v 1v 0 0 12v 0 5v a. v out1 , 100mv/div b. i lx1 , 10a/div c. lx1, 10v/div d. dl1, 5v/div refin1 = 1v to 1.2v to 1v skip = gnd dynamic output-voltage transition (skip mode-forced transition) MAX17007A/8 toc28 20 s/div a b c d 1.2v 1v 0 0 12v 0 5v a. v out1 , 100mv/div b. i lx2 , 10a/div i out1 = 1a refin1 = 1v to 1.2v to 1v skip = ref c. lx1, 10v/div d. dl1, 5v/div i out1 = 3a pin description typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = 5v, skip = gnd, t a = +25c, unless otherwise noted.) pin name function 1 ref 2v reference voltage output. bypass ref to gnd with a 2.2nf ceramic capacitor. the reference can source up to 100a. loading ref degrades output-voltage accuracy according to the ref load regulation error (see the typical operating characteristics ). the reference shuts down when both en1 and en2 are low. 2 ilim1 this four-level input determines the csh1 to csl1 current limit for smps1: v cc (5v) = 60mv current limit open (3.3v) = 45mv current limit ref (2v) = 30mv current limit gnd = 15mv current limit in combined mode, ilim1 sets the current-limit threshold for both sides. this four-level input determines the csh2 to csl2 current limit for smps2: v cc (5v) = 60mv current limit open (3.3v) = 45mv current limit ref (2v) = 30mv current limit gnd = 15mv current limit in combined mode, ilim2 is the current balance integrator (cci) output pin. connect a capacitor (c cci ) between cci and the output. the cci capacitor value depends on the ilim1 setting based on the following table: ilim1 c cci at ilim2 (pf) v cc (5v) 120 open (3.3v) 180 ref (2v) 220 3 ilim2 (cci) gnd 470 4 v cc 5v analog supply input. bypass v cc from v dd using a 10 resistor, and to analog ground using a 1f ceramic capacitor.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 12 ______________________________________________________________________________________ pin description (continued) pin name function 5 skip pulse-skipping control input. this four-level input determines the mode of operation under normal steady-state conditions and dynamic output-voltage transitions: v dd (5v) = forced-pwm operation open (3.3v) = ultrasonic mode (without forced-pwm during transitions) ref (2v) = pulse-skipping mode (with forced-pwm during transitions) gnd = pulse-skipping mode (without forced-pwm during transitions) there are no dynamic transitions for smps2, so skip = 2v and skip = gnd have the same pulse- skipping behavior for smps2 without any forced-pwm transitions. in combined mode, the ultrasonic mode is disabled, and the skip = open (3.3v) setting is identical to the skip = gnd setting. 6 ton1 frequency-setting input for smps1. an external resistor between the input power source and ton1 sets the switching period (t sw1 ) of smps1: t sw1 = c ton (r ton1 + 6.5k ) where c ton = 16.26pf. ton1 is high impedance in shutdown. in combined mode, ton1 sets the switching period for both smps1 and smps2. 7 ton2 frequency-setting input for smps2. an external resistor between the input power source and ton2 sets the switching period (t sw2 ) of smps2: t sw2 = c ton (r ton2 + 6.5k ) where c ton = 16.26pf. set ton2 to a switching frequency different from ton1. a 10% to 30% difference in switching frequency between smps1 and smps2 is recommended. ton2 is high impedance in shutdown. in combined mode, ton2 may be left open. 8 refin1 external reference input for smps1. refin1 sets the feedback regulation voltage of csl1. smps1 includes an internal window comparator to detect refin1 voltage changes that are greater than 50mv (typ), allowing the controller to blank pgood1 and the fault protection, and force the output transition, if enabled. when refin1 is tied to v cc , smps1 regulates the output to 1.05v. in combined mode, refin1 sets the feedback regulation voltage of the combined output. 9 csl1 output-sense and negative current-sense input for smps1. when using the internal preset 1.05v feedback divider (refin1 = v cc ), the controller uses csl1 to sense the output voltage. connect to the negative terminal of the current-sense element. figure 14 describes two different current- sensing optionsusing accurate sense resistors or lossless inductor dcr sensing. 10 csh1 positive current-sense input for smps1. connect to the positive terminal of the current-sense element. figure 14 describes two different current-sensing optionsusing accurate sense resistors or lossless inductor dcr sensing. 11 en1 enable control input for smps1. connect to v cc for normal operation. pull en1 low to disable smps1. the controller slowly ramps down the output voltage to ground and after the target voltage reaches 0.1v, the controller forces dl1 low. when both en1 and en2 are low, the device enters the low-power shutdown state. in combined mode, en1 controls the combined smps output. en2 is unused and must be grounded. 12 pgood1 open-drain power-good output for smps1. pgood1 is low when the smps1 voltage is more than 200mv below or 300mv above the target voltage, during soft-start, and in shutdown. after the smps1 soft-start circuit has terminated, pgood1 becomes high impedance 200s after the output is in regulation. pgood1 is blanked (forced high-impedance state) when a dynamic refin1 transition is detected. 13 dh1 high-side gate-driver output for smps1. dh1 swings from lx1 to bst1. dh1 is low in shutdown.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 13 pin description (continued) pin name function 14 lx1 inductor connection for smps1. connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate driver. 15 bst1 bootstrap capacitor connection for smps1. the MAX17007A/max17008 include an internal boost switch/diode connected between v dd and bst1. connect to an external capacitor as shown in figure 1. 16 gnd ground. analog and power ground connection for the low-side gate driver of smps1. 17 dl1 low-side gate driver output for smps1. dl1 swings from gnd to v dd . dl1 is forced low after the shutdown sequence has completed. dl1 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that may be present. dl1 is forced low in v cc uvlo. 18 v dd 5v driver supply input. connect v dd to v cc through a 10 resistor. bypass to ground through a 2.2f or greater ceramic capacitor. v dd is internally connected to the bst diodes and the low-side gate drivers. 19 dl2 low-side gate-driver output for smps2. dl2 swings from pgnd to v dd . dl2 is forced low after the shutdown sequence has completed. dl2 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that may be present. dl2 is forced low in v cc uvlo. 20 pgnd power ground for the low-side gate driver of smps2 21 bst2 bootstrap capacitor connection for smps2. the MAX17007A/max17008 include an internal boost switch/ diode connected between v dd and bst2. connect to an external capacitor as shown in figure 1. 22 lx2 inductor connection for smps2. connect lx2 to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate driver. 23 dh2 high-side gate-driver output for smps2. dh2 swings from lx2 to bst2. dh2 is low in shutdown. 24 pgood2 open-drain power-good output for smps2. pgood2 is low when the fb2 voltage is more than 100mv below or 150mv above the target voltage, during soft-start, and in shutdown. after the smps2 soft-start circuit has terminated, pgood2 becomes high impedance 200s after the output is in regulation. in combined mode, pgood2 is not used and can be left open. 25 en2 smps2 enable input. connect to v cc for normal operation. pull en2 low to disable smps2. the controller slowly ramps down the output voltage to ground, and after the target voltage reaches 0.1v, the controller forces dl2 low. when both en1 and en2 are low, the device enters the low-power shutdown state. in combined mode, en2 is not used and should be connected to gnd. 26 csh2 positive current-sense input for smps2. connect to the positive terminal of the current-sense element. figure 14 describes two different current-sensing optionsusing accurate sense resistors or lossless inductor dcr sensing. 27 csl2 output-sense and negative current-sense input for smps2. when using the internal preset 1.5v feedback divider (fb2 = ref), the controller uses csl2 to sense the output voltage. connect to the negative terminal of the current-sense element. figure 14 describes two different current-sensing optionsusing accurate sense resistors or lossless inductor dcr sensing. 28 fb2 smps2 feedback input. adjust the smps2 voltage with a resistive voltage-divider between smps2 output and gnd. connect fb2 to ref for preset 1.5v output. tie fb2 to v cc to configure the MAX17007A/max17008 for combined-mode operation. ep exposed backside pad. connect to analog ground.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 14 ______________________________________________________________________________________ MAX17007A max17008 6 ton1 agnd r refin1 r refin2 16 c vcc 1 f r2 100k to system power-good r9 10 r ton1 220k r ntc1 10k r4 3.01k r ton2 180k c ref 2.2nf r refin3 gnd pwr pwr pwr agnd pwr agnd 2 ilim1 3 ilim2 (cci) 5 skip 11 en1 25 en2 1 ref r refin1 = 80.6k r refin2 = 121k r refin3 = 249k 8 refin1 12 pgood1 24 pgood2 7 ton2 15 bst1 13 dh1 14 lx1 17 dl1 n h1 n l1 20 pgnd 10 csh1 9 csl1 28 fb2 4 v cc 18 v dd ref ref +3.3v h = 1.0v l = 1.2v 4-level skip pin ref +5v connect to ref for fixed 1.5v output *lower input voltages require additional input capacitance. v in 7v to 20v ep power ground analog ground r1 100k c vdd 2.2 f c1 0.22 f c bst1 0.1 f pwr d l1 c in1 r3 1.5k c out1 2 x 330 f 12m l1 1 h, 16a, 3m v out1 1.2v/1.0v, 12a ilim1 ilim2 v cc open ref gnd r7 10 c2 1nf pwr c out1-cer 5 x 10 f ceramic v out2 1.5v, 12a r ntc2 10k r6 3.01k pwr agnd pwr 21 bst2 23 dh2 22 lx2 19 dl2 n h2 n l2 26 csh2 27 csl2 v in 7v to 20v c3 0.22 f c bst2 0.1 f pwr d l2 c in2 r5 1.5k c out2 2 x 330 f 12m l2 1 h, 16a, 3m r8 10 c4 1nf pwr c out2-cer 5 x 10 f ceramic current limit 60mv 45mv 30mv 15mv figure 1. MAX17007A/max17008 separate-mode standard application circuit
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 15 v out1 = 1.0v/1.2v at 12a (figure 1) v out = 1.5v at 12a (figure 1) component v in = 7v to 20v ton1 = 220 k (270khz) v in = 7v to 20v ton2 = 180 k (330khz) input capacitor (per phase) (2x) 10f, 25v taiyo yuden tmk432bj106km (2x) 10f, 25v taiyo yuden tmk432bj106km output capacitor (2x) 330f, 2.5v, 12m , c case sanyo 2r5tpe330mcc2 (2x) 330f, 2.5v, 12m , c case sanyo 2r5tpe330mcc2 inductor 1h, 3.25m , 16a wrth electronics 7443552100 1h, 3.25m , 16a wrth electronics 7443552100 schottky diode 2a, 30v schottky diode (sma) nihon ec21qs03l central semiconductor cmsh2-40m 2a, 30v schottky diode (sma) nihon ec21qs03l central semiconductor cmsh2-40m high-side mosfet fairchild semiconductor (1x) fds8690 8.6m /11.4m (typ/max) fairchild semiconductor (1x) fds8690 8.6m /11.4m (typ/max) low-side mosfet fairchild semiconductor (1x) fds8670 4.2m /5m (typ/max) fairchild semiconductor (1x) fds8670 4.2m /5m (typ/max) table 1. component selection for standard applications manufacturer website manufacturer website avx corp. www.avxcorp.com pulse engineering www.pulseeng.com bi technologies www.bitechnologies.com r enesas technology corp. www.renesas.com central semiconductor corp. www.centralsemi.com sanyo electric company, ltd. www.sanyodevice.com fairchild semiconductor www.fairchildsemi.com siliconix (vishay) www.vishay.com international rectifier www.irf.com sumida corp. www.sumida.com kemet corp. www.kemet.com taiyo yuden www.t-yuden.com nec tokin america, inc. www.nec-tokinamerica.com tdk corp. www.component.tdk.com panasonic corp. www.panasonic.com toko america, inc. www.tokoam.com table 2. component suppliers detailed description the MAX17007A/max17008 standard application circuit (figure 1) generates the 1v to 1.2v/12a and 1.5v/12a chipset voltages in a notebook computer. the input sup- ply range is 7v to 20v for the specific application. table 1 lists component selections, while table 2 lists the com- ponent manufacturers. figure 2 shows the combined- mode standard application circuit and figure 3 is the MAX17007A/max17008 functional diagram. the MAX17007A/max17008 contain two constant on- time step-down controllers designed for low-voltage power supplies. the two smpss can also be combined to operate as a two-phase high-current single-output regulator. constant on-time quick-pwm operation pro- vides fast response to load transients and handles wide i/o voltage ratios with ease, while maintaining a relatively constant switching frequency. the switching frequency can be adjusted between 200khz and 600khz with external resistors. differential output current sensing allows output sense-resistor sensing for an accurate cur- rent-limit, lossless inductor dcr current sensing for lower power dissipation while maintaining 0.7% output accura- cy. overvoltage (MAX17007A) and undervoltage protec- tion and accurate user-selectable current limits (four different levels) ensure robust operations. the MAX17007A/max17008 feature a special com- bined-mode configuration that allows higher current outputs to be supported. a current-balance integrator maintains equal currents in the two phases, improving efficiency and power distribution.
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 16 ______________________________________________________________________________________ MAX17007A max17008 6 x ton1 agnd r refin1 r refin2 16 c vcc 1 f pgood2 not used iin combined mode ilim2 functions as cci output in combined mode en2 must be grounded r9 10 r ton1 220k r ntc1 10k r4 3.01k c ref 2.2nf c cci 220pf r refin3 gnd pwr pwr pwr agnd pwr agnd 2 ilim1 3 ilim2 (cci) 5 skip 11 en1 25 en2 1 ref r refin1 = 80.6k r refin2 = 121k r refin3 = 249k 8 refin1 12 pgood1 24 pgood2 7 ton2 15 bst1 13 dh1 14 lx1 17 dl1 n h1 n l1 20 pgnd 10 csh1 9 csl1 28 fb2 4 v cc 18 v dd ref v out +3.3v h = 1.0v l = 1.2v +5v +5v connect to 5v for combined mode operation *lower input voltages require additional input capacitance. v in 7v to 20v ep power ground analog ground r1 100k c vdd 2.2 f c1 0.22 f c bst1 0.1 f pwr d l1 c in1 r3 1.5k c out1 4 x 330 f 12m l1 1 h, 16a, 3m v out1 1.2v/1.0v, 24a ilim pin v cc open ref gnd r7 10 c2 1nf pwr c out1-cer 10 x 10 f ceramic r ntc2 10k r6 3.01k pwr agnd 21 bst2 23 dh2 22 lx2 19 dl2 n h2 n l2 26 csh2 27 csl2 v in 7v to 20v c3 0.22 f c bst2 0.1 f pwr d l2 c in2 r5 1.5k l2 1 h, 16a, 3m r8 10 c4 1nf current limit c cci (pf) 60mv 45mv 30mv 15mv 120 180 220 470 figure 2. MAX17007A/max17008 combined-mode standard application circuit
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 17 MAX17007A max17008 power-good and fault protection 2 (figure 13) pwm controller 2 (figure 4) current limit 2 (figure 8) smps2 target decode (figure 9b) mux 2.0v ref pgood2 combine (fb2 = v cc ) fb2 csh2 csl2 ilim2 en2 lx2 current- sense gain valley current limit dh2 bst2 pgnd dl2 v dd csl2 target2 g m g m power-good and fault protection 1 (figure 13) pwm controller 1 (figure 4) current limit 1 (figure 8) smps1 target decode (figure 9a) mux pgood1 ref v cc refin1 csh1 csl1 ilim1 skip ton1 ton2 en1 lx1 current- sense gain valley current limit dh1 bst1 gnd dl1 csl1 g m g m target1 fault1 fault2 v dd current balance combine (fb2 = v cc ) combine (fb2 = v cc ) combine (fb2 = v cc ) figure 3. MAX17007A/max17008 functional diagram
+5v bias supply (v cc , v dd ) the MAX17007A/max17008 require an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebooks 95%-efficient 5v system sup- ply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to sup- ply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator such as the max1615. the 5v bias supply powers both the pwm controllers and internal gate-drive power, so the maximum current drawn depends on the external mosfets gate capaci- tance, and the selected switching frequency: i bias = i q + f sw1 q g(smps1) + f sw2 q g(smps2) = 4ma to 40ma (typ) bypass v cc with a 1f or greater ceramic capacitor to the analog ground. bypass v dd with a 2.2f or greater ceramic capacitor to the power ground. v cc and v dd should be separated with a 10 resistor (figure 1). 2v reference the 2v reference is accurate to 1% over temperature and load, making ref useful as a precision system ref- erence. bypass ref to gnd with a 2.2nf. the refer- ence sources up to 100a and sinks 10a to support external loads. combined-mode operation (fb2 = v cc ) combined-mode operation allows the MAX17007A/ max17008 to support even higher output currents by sharing the load current between two phases, distribut- ing the power dissipation over several power compo- nents to improve the efficiency. the MAX17007A/ max17008 are configured in combined mode by con- necting fb2 to v cc . see figure 2 for the combined- mode standard application circuit. table 3 lists the pin function differences between com- bined mode and separate mode. see the pin description for additional details. MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 18 ______________________________________________________________________________________ pin combined mode separate mode fb2 connect to v cc to configure MAX17007A/max17008 for combined-mode operation connect to ref for preset 1.5v, or use a resistor- divider to set the smps2 output voltage refin1 sets the combined output voltagedynamic, fixed, and preset voltages supported sets the smps1 output voltagedynamic, fixed, and preset voltages supported en1 enables/disables combined output enables/disables smps1 en2 not used; connect to gnd enables/disables smps2 pgood1 power-good indicator for combined output voltage power-good indicator for smps1 pgood2 not used; can be left open power-good indicator for smps2 ton1 sets the per-phase switching frequency for both smpss sets the switching frequency for smps1 ton2 not used; leave open sets the switching frequency for smps2 ilim1 sets the per-phase current limit for both smpss sets smps1 current limit ilim2 (cci) current-balance integrator output; connect a capacitor from cci to the output sets smps2 current limit skip only three distinct modes of operation; ultrasonic mode not supported supports all four modes of operation table 3. pin function in combined and separate modes
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 19 smps detailed description free-running constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feed-forward. this architecture relies on the output filter capacitors esr to act as a current- sense resistor, so the output ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one- shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (150ns typ). the on-time one-shot is triggered if the error compara- tor is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one- shot has timed out. figure 4 is the pwm controller block diagram. on-time one-shot the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. in independent mode, the high-side switch on-time is inversely propor- tional to the battery voltage as sensed by the ton1 and ton2 inputs, and proportional to the voltages on csl1 and csl2 pins: smps1 on-time t on1 = t sw1 (v csl1 /v in ) smps2 on-time t on2 = t sw2 (v csl2 /v in ) where t sw1 (switching period of smps1) is set by the resistance between ton1 and v in , t sw2 is set by the resistance between ton2 and v in . this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. MAX17007A max17008 csl or cci dh driver dl driver on-time compute integrator (ccv) ton trig one-shot q error amplifier internal fb zero crossing valley current limit ov fault amplified current sense slope comp t on r s q r s q target t off(min) trig q figure 4. pwm controller block diagram
MAX17007A/max17008 switching frequency the MAX17007A/max17008 feature independent resis- tor-programmable switching frequencies for each smps, providing flexibility for applications where one smps operates at a lower switching frequency when connected to a high-voltage input rail while the other smps operates at a higher switching frequency when connected to a lower voltage rail as a second-stage regulator. connect a resistor (r ton ) between ton and v in to set the switching period t sw = 1/f sw : t sw1 = c ton (r ton1 + 6.5k ) t sw2 = c ton (r ton2 + 6.5k ) where c ton = 16.26pf. a 97.5k to 302.5k corre- sponds to switching periods of 1.67s (600khz) to 5s (200khz) for smps1 and smps2. high-frequency (600khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower volt- age supply. low-frequency (200khz) operation offers the best overall efficiency at the expense of component size and board space. for continuous conduction operation, the actual switching frequency can be estimated by: where v dis is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and printed-circuit board (pcb) resis- tances; v chg is the sum of the resistances in the charging path, including the high-side switch, inductor, and pcb resistances; and t on is the on-time calculated by the on-time block. when operating in separate mode, it is recommended that both smps switching frequencies be set apart by 10% to 30% to prevent the two sides from beating against each other. combined-mode on-time one-shot in combined mode (fb2 = v cc ), ton1 sets the on- time, and hence the switching frequency, for both smps. the on-time is programmed using the ton1 equation, which sets the switching frequency per phase. the effec- tive switching frequency as seen on the input and output capacitors is twice the per-phase frequency. combined-mode current balance in combined mode, the one-shot for smps2 varies the on-time in response to the input voltage and the differ- ence between the smps1 and smps2 inductor cur- rents. the smps1 one-shot in combined mode behaves the same way as it does in separate mode. as such, smps2 regulates the current balance, while smps1 regulates the voltage. two identical transconductance amplifiers integrate the difference between smps1 and smps2 current-sense signals. the summed output is internally connected to cci, allowing adjustment of the integration time con- stant with a compensation network (usually a capacitor) connected between cci and the output. the resulting compensation current and voltage are determined by the following equations: i cci = g m [(v csh1 - v csl1 ) - (v csh2 - v csl2 )] v cci = v out + i cci z cci where z cci is the impedance at the cci output. the smps2 on-time one-shot uses this integrated signal (v cci ) to set the smps2 high-side mosfets on-time. when smps1 and smps2 current-sense signals (v csh1 - v csl1 and v csh2 - v csl2 ) become unbalanced, the transconductance amplifiers adjust the smps2 on-time, which increases or decreases the smps2 inductor cur- rent until the current-sense signals are properly bal- anced. in combined mode, the smps2 on-time is given by: smps2 on-time t on2 = t sw2 (v cci /v in ) smps enable controls (en1, en2) en1 and en2 provide independent control of output soft-start and soft-shutdown. this allows flexible control of startup and shutdown sequencing. the outputs can be started simultaneously, sequentially, or indepen- dently. to provide sequential startup, connect en of one regulator to pgood of the other. for example, with en1 connected to pgood2, out1 soft-starts after out2 is in regulation. when configured in separate mode, the two outputs are independent. a fault at one output does not trigger shutdown of the other. when configured in combined mode (fb2 = v cc ), en1 is the master control input that enables/disables the combined output, while en2 has no function and must be connected to gnd. the startup slew rate follows that of smps1. toggle en low to clear the overvoltage, undervoltage, and thermal-fault latches. f vv tvv sw out dis on in chg = + + () dual and combinable qpwm graphics core controllers for notebook computers 20 ______________________________________________________________________________________
soft-start soft-start begins when en is driven high and ref is in regulation. during soft-start, the output is ramped up from 0v to the final set voltage at 1.3mv/s slew rate for smps1, and 0.65mv/s for smps2, reducing the inrush current and providing a predictable ramp-up time for power sequencing: the soft-start circuitry does not use a variable current limit, so full output current is available immediately. the respective pgood becomes high impedance approxi- mately 200s after the target voltage has been reached. the MAX17007A/max17008 automatically use pulse-skipping mode during soft-start and use forced-pwm mode during soft-shutdown, regardless of the skip configuration. for automatic startup, the battery voltage should be present before v cc . if the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling en or cycling the v cc power supply below 0.5v. soft-shutdown soft-shutdown begins when the system pulls en low, an output undervoltage fault, or a thermal fault. during soft-shutdown, the respective pgood is pulled low immediately and the output voltage ramps down with the same startup slew rate for the respective outputs. after the controller reaches the 0v target, the drivers are disabled (dl_ and dh_ pulled low) and the internal 10 discharge on csl_ activated. the MAX17007A/ max17008 shut down completely when both en are lowthe reference turns off after both smpss have reached the 0v target, and the supply current drops to about 1a (max). slowly discharging the output capacitors by slewing the output over a long period of time (typically 0.5ms to 2ms) keeps the average negative inductor current low (damped response), thereby preventing the negative output-voltage excursion that occurs when the con- troller discharges the output quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. modes of operation forced-pwm mode ( s s k k i i p p = 5v) the low-noise forced-pwm mode ( skip = 5v) disables the zero-crossing comparator, which controls the low- side switch on-time. this forces the low-side gate-drive waveform to constantly be the complement of the high- side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factor of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant. however, forced-pwm operation comes at a cost: the no-load 5v bias current remains between 2ma to 5ma, depending on the switching frequency. the MAX17007A/max17008 automatically use forced- pwm operation during shutdown, regardless of the skip configuration. automatic pulse-skipping mode ( s s k k i i p p = gnd or 2v) in skip mode ( skip = gnd or 2v), an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator threshold is set by the differential across csl_ and csh_. dc output-accuracy specifications refer to the threshold of the error comparator. when the inductor is in continuous conduction, the MAX17007A/max17008 regulate the valley of the output ripple, so the actual dc output volt- age is higher than the trip level by 50% of the output rip- ple voltage. in discontinuous conduction ( skip = gnd or 2v and i out < i load(skip) ), the output voltage has a dc regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compen- sation. however, the internal integrator corrects for most of it, resulting in very little load regulation. when skip = 2v, the MAX17007A/max17008 use forced- pwm operation during all dynamic output-voltage transi- tions until 100s after the transition has been completedrefin1 and the internal target are within 50mv (typ) and an error-amplifier transition is detected. since smps2 does not support dynamic transitions, skip = 2v and skip = gnd have the same pulse-skipping behavior without any forced-pwm transitions. tt v sr v mv s start shdn fb ss fb 22 2 2 2 065 === ./ tt v sr v mv s start shdn refin ss refin 11 1 1 1 13 == = ./ MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 21
MAX17007A/max17008 when skip is pulled to gnd, the MAX17007A/max17008 remain in pulse-skipping mode. since the output is not able to sink current, the timing for negative dynamic out- put-voltage transitions depends on the load current and output capacitance. letting the output voltage drift down is typically recommended in order to reduce the potential for audible noise since this eliminates the input current surge during negative output-voltage transitions. figure 5 shows the pulse-skipping/discontinuous crossover point. ultrasonic mode ( s s k k i i p p = open = 3.3v) leaving skip unconnected or connecting skip to 3.3v activates a unique pulse-skipping mode with a mini- mum switching frequency of 25khz. this ultrasonic pulse-skipping mode eliminates audio-frequency mod- ulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultra- sonic mode, the controller automatically transitions to fixed-frequency pwm operation when the load reaches the same critical conduction point (i load(skip) ) that occurs when normally pulse skipping. an ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 30s. once triggered, the ultrasonic controller pulls dl high, turning on the low-side mosfet to induce a negative inductor current (figure 6). after the inductor current reaches the negative ultrasonic current threshold, the controller turns off the low-side mosfet (dl pulled low) and triggers a constant on-time (dh driven high). when the on-time has expired, the controller reenables the low-side mosfet until the controller detects that the inductor current dropped below the zero-crossing threshold. starting with a dl pulse greatly reduces the peak output voltage when compared to starting with a dh pulse. the output voltage at the beginning of the ultrasonic pulse determines the negative ultrasonic current thresh- old, resulting in the following equations for smps1: (smps1 adjustable mode) (smps1 preset mode) where v csl1 > v refin1 in adjustable mode, v csl1 > 1.05v in preset mode, and r cs1 is the current-sense resistance seen across csh1 to csl1. similarly for smps2: (smps2 adjustable mode) (smps2 preset mode) where v csl2 > 0.7v in adjustable mode, v csl2 > 1.5v in preset mode, and r cs2 is the current-sense resis- tance seen across csh2 to csl2. in combined mode, ultrasonic mode setting is disabled, and the skip = open (3.3v) setting is identical to the skip = gnd setting. virvv isonic l cs csl 222 2 15 065 .. == () - virvv isonic l cs fb 222 2 07 065 .. == () - vir vv isonic l cs csl 111 1 105 065 .. == () - virvv isonic l cs refin csl 111 1 1 065 . == () - dual and combinable qpwm graphics core controllers for notebook computers 22 ______________________________________________________________________________________ inductor current i load = i peak /2 on-time 0 time i peak l v in - v out i t = figure 5. pulse-skipping/discontinuous crossover point on-time (t on ) i sonic 0 zero-crossing detection inductor current 40 s (max) figure 6. ultrasonic waveform
valley current-limit protection the current-limit circuit employs a unique valley cur- rent-sensing algorithm that senses the inductor current across the output current-sense elementinductor dcr or current-sense resistor, which generates a volt- age between csh_ and csl_. if the current exceeds the valley current-limit threshold during the low-side mosfet conduction time, the pwm controller is not allowed to initiate a new cycle. the valley current-limit threshold is set by the four-level ilim_ pin, with selec- table limits of 15mv, 30mv, 45mv, and 60mv. the actual peak current is greater than the valley cur- rent-limit threshold by an amount equal to the inductor ripple current (figure 7). therefore, the exact current- limit characteristic and maximum load capability are a function of the inductor value and battery voltage. when combined with the undervoltage protection cir- cuit, this current-limit method is effective in almost every circumstance. see figure 8. in forced-pwm mode, the MAX17007A/max17008 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 120% of the positive current limit. in combined mode, ilim1 sets the per-phase current limit for both phases. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder- ate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate driver (dh) sources and sinks 1.2a, and the low-side gate driver (dl) sources 1.0a and sinks 2.4a. this ensures robust gate drive for high-current applications. the dh floating high-side mosfet driver is powered by internal boost switch charge pumps at bst, while the dl synchro- nous-rectifier driver is powered directly by the 5v bias supply (v dd ). MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 23 inductor current i limit i load 0 time i peak i lim(val) = i load(max) 1- lir 2 () figure 7. valley current-limit threshold point csh ilim csl skip zero crossing valley current limit quad-level decode current- sense gain figure 8. current-limit block diagram
MAX17007A/max17008 output voltage the MAX17007A/max17008 feature preset and adjustable output voltages for both smpss, and dynam- ic output voltages for smps1. in combined mode, the output voltage is set by refin1, and all features for smps1 output-voltage configuration and dynamic volt- age changes apply to the combined output. figure 9 is the smps target decode block diagram. preset/adjustable output voltages (dual-mode feedback) connect refin1 to v cc to set the smps1 voltage to preset 1.05v. connect fb2 to ref to set the smps2 voltage to preset 1.5v. the smps1 output voltage can be adjusted up to 2v by changing refin1 voltage with- out using an external resistive voltage-divider. the out- put voltage of smps2 can be adjusted with an external resistive voltage-divider between csl2 and gnd with the center tap connected to fb2 (figure 10). choose r fb2lo (resistance from fb2 to gnd) to be approxi- mately 10k and solve for r fb2hi (resistance from csl2 to fb2) using the equation: the MAX17007A/max17008 regulate the valley of the output ripple, so the actual dc output voltage is higher than the slope compensated target by 50% of the out- put ripple voltage. under steady-state conditions, the MAX17007A/max17008s internal integrator corrects for this 50% output ripple voltage error, resulting in an out- put-voltage accuracy that is dependent only on the off- set voltage of the integrator amplifier provided in the electrical characteristics table. dynamic output voltages (refin1) the MAX17007A/max17008 regulate the output to the voltage set at refin1. by changing the voltage at refin1 (figure 11), the MAX17007A/max17008 can be used in applications that require dynamic output volt- age changes between two set points. for a step-volt- age change at refin1, the rate of change of the output voltage is limited either by the internal 9.5mv/s slew- rate circuit or by the component selectioninductor current ramp, the total output capacitance, the current limit, and the load during the transitionwhichever is slower. the total output capacitance determines how much current is needed to change the output voltage, while the inductor limits the current ramp rate. rr v v fb hi fb lo csl 22 2 07 1 = ? ? ? ? ? ? . - dual and combinable qpwm graphics core controllers for notebook computers 24 ______________________________________________________________________________________ v cc - 1v fb2 ref - 0.3v target1 combine (fb2 = v cc ) preset (fb1 = v cc ) preset (fb2 = ref) (b) smps2 target decode target2 ref (2.0v) 0.7v 1.5v 5r 8r 7r refin1 (a) smps1 target decode target1 ref (2.0v) 1.05v 9.5r 10.5r v cc - 1v figure 9. smps target decode block diagram MAX17007A max17008 dl2 gnd lx2 l2 fb2 csl2 csh2 r fb2lo c out2 r sense2 r fb2hi n l2 figure 10. setting v out2 with a resistive voltage-divider
additional load current can slow down the output volt- age change during a positive refin1 voltage change, and can speed up the output voltage change during a negative refin1 voltage change. automatic fault blanking (smps1) when the MAX17007A/max17008 detect that the inter- nal target and refin1 are more than 50mv (typ) apart, the controller automatically blanks pgood1, blanks the uvp protection, and sets the ovp threshold to max ref +300mv. the blanking remains until 1) the internal target and refin1 are within 50mv of each other, and 2) an edge is detected on the error amplifier signifying that the output is in regulation. this prevents the system or internal fault protection from shutting down the controller during transitions. figure 11 shows the dynamic refin1 transit ion ( skip = gnd) and figure 12 shows the dynamic refin1 transition ( skip = ref). MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 25 internal pwm control refin1 blank high-z skip lx1 set to ref + 300mv v out1 internal target1 actual v out1 blank high-z dynamic refin1 window target1 + 300mv -50mv pgood1 lower threshold + uvp1 pgood1 upper threshold + ovp1 no pulses: v out1 > v target1 figure 11. dynamic refin1 transition ( skip = gnd) internal pwm control v out1 refin1 blank high-z skip lx1 ref + 300mv internal target1 = actual v out1 blank high-z skip 200 s 200 s +50mv -50mv pgood1 lower threshold + uvp1 pgood1 upper threshold + ovp1 pwm pwm target1 + 300mv target1 + 300mv dynamic refin1 window figure 12. dynamic refin1 transition ( skip = ref)
MAX17007A/max17008 internal integration an integrator amplifier forces the dc average of the fb voltage to equal the target voltage. this internal amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 4), allowing accurate dc output-voltage regulation regardless of the compensated feedback ripple voltage and internal slope- compensation variation. the integrator amplifier has the ability to shift the output voltage by 140mv (typ). the MAX17007A/max17008 disable the integrator by connecting the amplifier inputs together at the begin- ning of all dynamic refin1 transitions done in pulse- skipping mode. the integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). power-good outputs (pgood) and fault protection pgood_ is the open-drain output that continuously monitors the respective output voltage for undervoltage and overvoltage conditions. the respective pgood_ is actively held low in shutdown (en_ = gnd) during soft- start and soft-shutdown. approximately 200s (typ) after the soft-start terminates, pgood_ becomes high impedance as long as the respective output voltage is in regulation. pgood1 goes low if the output voltage drops 200mv below the target voltage (refin1 or fixed 1.05v), or rises 300mv above the target voltage (refin1 or fixed 1.05v), or the smps1 controller is shut down. in adjustable mode, pgood2 goes low if the feedback voltage drops 100mv below the target voltage (0.7v), or rises 150mv above the target voltage (0.7v), or the smps2 controller is shut down. in preset mode (fixed 1.5v), the pgood2 thresholds are -200mv and +300mv. for a logic-level pgood output voltage, connect an external pullup resistor between pgood and v dd . a 100k pullup resistor works well in most applications. see figure 13. overvoltage protection (ovp, MAX17007A only) when the internal feedback voltage rises above the overvoltage threshold, the ovp comparator immediate- ly pulls dh low and forces dl high, pulls pgood low, sets the fault latch, and disables the faulted smps con- troller. toggle en or cycle v cc power below the v cc por to clear the fault latch and restart the controller. the overvoltage thresholds are +300mv for smps1 (fixed 1.05v and adjustable refin1), +300mv for smps2 in preset mode (fixed 1.5v output), and +150mv for smps2 in adjustable mode (0.7v feedback). an ov fault on one side does not affect the other side. dual and combinable qpwm graphics core controllers for notebook computers 26 ______________________________________________________________________________________ target + v ovp target - v uvp csl or fb fault ovp enabled (MAX17007A only) fault latch one shot 200 s power-good in clk out ovp uvp en soft-start complete note: only the MAX17007A has ovp function enabled. figure 13. power-good and fault protection
undervoltage protection (uvp) when the feedback voltage drops below the undervolt- age threshold, the controller immediately pulls pgood low and triggers a 200s one-shot timer. if the feed- back voltage remains below the undervoltage fault threshold for the entire 200s, then the undervoltage fault latch of the faulted smps is set and that smps begins its shutdown sequence. when the internal target voltage drops below 0.1v, the MAX17007A/max17008 force dl low for the faulted smps. toggle en or cycle v cc power below v cc por to clear the fault latch and restart the controller. the undervoltage thresholds are -200mv for smps1 (fixed 1.05v and adjustable refin1), -200mv for smps2 in preset mode (fixed 1.5v output), and -100mv for smps2 in adjustable mode (0.7v feedback). a uv fault on one side does not affect the other side. thermal-fault protection (t shdn ) the MAX17007A/max17008 feature a thermal-fault pro- tection circuit. when the junction temperature rises above +160c, a thermal sensor activates the fault latch, pulls pgood low, and shuts down the controller. both dl and dh are pulled low. toggle en or cycle v cc power below v cc por to reactivate the controller after the junction temperature cools by 15c. v cc por and uvlo each smps of the MAX17007A/max17008 is enabled when its respective en is driven high. on the first rising en, the reference powers up first. once the reference exceeds its undervoltage lockout (uvlo) threshold (~ 60s), the internal analog blocks are turned on and masked by a 140s one-shot delay in order to allow the bias circuitry and analog blocks enough time to settle to their proper states. with the control circuitry reliably powered up, the pwm controller begins switching. the second rising en, if controlled separately, also has the 140s one-shot delay before its first dh pulse. power-on reset (por) occurs when v cc rises above approximately 3v, resetting the fault latch and preparing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the system enables the controller, v cc exceeds 4.25v, and either en is dri- ven high. with the reference in regulation, the controller ramps the output voltage to the target voltage with a 1.3mv/s slew rate for smps1 and 0.65mv/s for smps2. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions. to protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (dl and dh pulled low). MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 27 mode controller state driver state shutdown (en_ = high to low) output uvp (latched) thermal fault (latched) voltage soft-shutdown initiated. error amplifier target slowly ramped down to gnd. dl_ low and dh_ low after soft-shutdown completed, internal 10 discharge on csl_ activated. (target < 0.1v.) output ovp (latched) controller shuts down and internal target slews down. controller remains off until en_ toggled or v cc power cycled. dl_ immediately forced high, dh_ pulled low (high-side mosfet disabled). v cc uvlo falling edge controller shuts down and the internal target slews down. controller remains off until v cc rises back above uvlo threshold. dl_ low, dh_ low, internal 10 discharge on csl_ activated. v cc uvlo rising edge smps controller enabled (assuming en_ pulled high). dl_, dh_ switching. v cc por smps inactive. dl_ low. table 4. fault protection and shutdown operation
MAX17007A/max17008 quick-pwm design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case input supply voltage allowed by the notebooks ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stress- es and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. most notebook loads generally exhibit i load = i load(max) x 80%. switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the per-phase switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: for example: i load(max) = 15a, v in = 12v, v out = 1.5v, f sw = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): in combined mode, i load(max) is the per-phase maxi- mum current, which is half the actual maximum load current for the combined output. transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. the worst-case output sag voltage can be determined by: where t off(min) is the minimum off-time (see the electrical characteristics table). the amount of overshoot due to stored inductor energy can be calculated as: where n ph is the number of active phases per output. n ph is 1 for separate mode, and n ph is 2 for com- bined-mode operation. v il nc v soar load max ph out out () () 2 2 v vt v t sag out sw in off m = () ? ? ? ? ? ? + li load(max) 2 ( i in out out in out in sw o cv vv v tt ) ? ? ? ? ? ? ? ? ? ? ? ? 2 - - f ff min () ? ? ? ? ? ? ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv khz a v v = ? ? ? ? ? ? ? ? 12 1 5 300 15 0 3 15 12 -. . . ? ? ? ? ? = 097 .h l vv fi lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? - () ? ? ? dual and combinable qpwm graphics core controllers for notebook computers 28 ______________________________________________________________________________________
setting the valley current limit the minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i limit(low) equals the minimum current-limit threshold voltage divided by the output sense element (inductor dcr or sense resistor). the four-level ilim setting sets a valley current limit of 15mv, 30mv, 45mv, or 60mv across the csh_ to csl_ differential input. special attention must be made to the tolerance and thermal variation of the on-resistance in the case of dcr sensing. use the worst-case maximum value for r dcr from the inductor data sheet, and add some mar- gin for the rise in r dcr with temperature. a good gen- eral rule is to allow 0.5% additional resistance for each c of temperature rise, which must be included in the design margin unless the design includes an ntc ther- mistor in the dcr network to thermally compensate the current-limit threshold. the current-sense method (figure 14) and magnitude determine the achievable current-limit accuracy and power loss. the sense resistor can be determined by: r sense_ = v lim_ /i limit_ for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 14a. this configuration constantly monitors the inductor current, allowing accurate current-limit protection. however, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. this parasitic inductance (l esl ) can be can- celled by adding an rc circuit across the sense resis- tor with an equivalent time constant: alternatively, low-cost applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series rc cir- cuit across the inductor (figure 14b) with an equivalent time constant: and: where r cs is the required current-sense resistance and r dcr is the inductors series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + 2 12 cr l r eq eq esl sense = i i n lir limit low load max ph () () > ? ? ? ? ? ? 1 2 - MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 29 sense resistor l MAX17007A max17008 c out input (v in ) c in csl_ csh_ pgnd dl_ dh_ lx_ c eq r eq n h n l d l l esl r sense c eq r eq = l esl r sense a) output series resistor sensing figure 14. current-sense configurations (sheet 1 of 2)
MAX17007A/max17008 output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in core and chipset converters and other applications where the output is subject to large-load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in low-power applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitors esr. the maximum esr to meet ripple requirements is: where f sw is the switching frequency. with most chemistries (polymer, tantalum, aluminum, electrolytic), the actual capacitance value required relates to the physical size needed to achieve low esr and the chemistry limits of the selected capacitor tech- nology. ceramic capacitors provide low esr, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response sec- tion). thus, the output capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. esr vs. voltage rating) and cost. output capacitor stability considerations for quick-pwm controllers, stability is determined by the in-phase feedback ripple relative to the switching frequen- cy, which is typically dominated by the output esr. the boundary of instability is given by the following equation: where c out is the total output capacitance, r esr is the total esr of the output capacitors, r cs is the current- sense resistance, and a cs is the current-sense gain as determined by the ilim setting. a cs equals 2, 2.67, 4, and 8 for ilim settings of 5v, 3.3v, 2v, and gnd, respectively. for a 300khz application, the effective zero frequency must be well below 95khz, preferably below 50khz. for the standard application circuit with ceramic output capacitors, the output ripple cannot be relied upon to be in phase with the inductor current due to the low esr of the ceramic capacitors. stability is mainly dependent on the current-sense gain. with ilim = 2v, a cs = 4, and an effective current-sense resistance of approximately 3.5m , then the esr zero works out to: 1/[2 x (2 x 330f + 5 x 10f) x 4 x 3.5m ] = 16khz this is well within the stability requirements. rr ar eff esr cs cs =+ r fc eff sw out 1 2 f rc sw eff out 1 2 r vf l vv v v esr in sw in out out ripple () ? ? ? ? ? ? ? ? - rr v i esr pcb step load max + () () dual and combinable qpwm graphics core controllers for notebook computers 30 ______________________________________________________________________________________ MAX17007A max17008 c out input (v in ) c in b) lossless inductor sensing for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. csl_ csh_ pgnd dl_ dh_ lx_ c eq r1 r2 n h n l d l l inductor r dcr r cs = r2 r dcr r1 + r2 r dcr = l [ 1 + 1 ] c eq r1 r2 figure 14. current-sense configurations (sheet 2 of 2)
when only using ceramic output capacitors, output overshoot (v soar ) typically determines the minimum output capacitance requirement. their relatively low capacitance value can allow significant output over- shoot when stepping from full-load to no-load condi- tions, unless designed with a small inductance value and high switching frequency to minimize the energy transferred from the inductor to the capacitor during load-step recovery. unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the i rms requirements can be determined by the fol- lowing equation for a single-phase application: in combined mode, the input rms current simplifies to: where i load is the combined output current of both phases. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either con- figuration, choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the loss- es at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems might occur (see the mosfet gate drivers (dh, dl) section). mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issue until the input is greater than approximately 15v. pd nh sistive v v ir out in min load ds on (re ) () () = ? ? ? ? ? ? () 2 i i v v rms load in out = ? ? ? ? ? ? () 2 2v-v in out i i v vv i v vv v rms load out in out load out in out in = ? () +? () 1 2 112 2 22 MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 31
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers 32 ______________________________________________________________________________________ calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mos- fet, and i gate is the peak gate-drive source/sink cur- rent (2.4a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, you can over design the circuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. select a diode that can handle the load current during the dead times. this diode is optional and can be removed if effi- ciency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (2) irf7811w n-channel mosfets are used on the high side. according to the manufacturers data sheet, a sin- gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.22f ceramic capacitor. applications information minimum input voltage requirements and dropout performance the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable minimum off-time one-shot. for best dropout perfor- mance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propa- gation delays introduce an error to the on-times. this error is greater at higher frequencies. also, keep in mind that transient response performance of buck reg- ulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the transient response section (the v sag equation) in the quick-pwm design procedure section). c nc mv f bst = = 224 200 024 . c nq mv bst gate = 200 ii i i i lir load valley max inductor valley max load max =+ ? ? ? ? ? ? =+ ? ? ? ? ? ? () () () 2 2 pd nl sistive v v ir out in max load ds on (re ) () () =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2 pd nhswitching v i f q i in max load sw gsw gate () () () = ? ? ? ? ? ? ? + c oss v vf in max sw () 2 2
in a single-phase configuration, the absolute point of dropout is when the inductor current ramps down dur- ing the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down is an indicator of the ability to slew the inductor current higher in response to increased load and must always be greater than 1. as h approaches 1the absolute minimum dropout pointthe inductor current cannot increase as much during each switching cycle, and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v chg is the parasitic voltage drop in the charge path (see the on-time one-shot section), and t off(min) is from the electrical characteristics table. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required min- imum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example: v out = 1.5v f sw = 300khz t off(min) = 250ns v chg = 150mv (10a load) h = 1.5: calculating again with h = 1 gives the absolute limit of dropout: therefore, v in must be greater than 1.78v, even with very large output capacitance, and a practical input volt- age with reasonable output capacitance would be 2.0v. pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. ? connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of the quick-pwm controller. this includes the v cc bypass capacitor, ref bypass capacitors, refin1 components, and feedback compensation/dividers. ? keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mil- liohm of excess trace resistance causes a measur- able efficiency penalty. ? keep the high current, gate-driver traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes away from sensi- tive analog areas (ref, refin1, fb2, csh, and csl). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and anode of the low-side schottky). if possi- ble, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). v vmv s khz in min () . (. . ) = + ? ? ? 1 5 150 1 0 25 1 0 300 - ? ? ? ? = 178 .v v vmv s khz in min () . (. . ) = + ? ? ? 1 5 150 1 0 25 1 5 300 - ? ? ? ? = 186 .v v vv ht f in min out chg off min sw () () = () ? ? ? ? ? ? ? + - 1 ? ? MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 33
MAX17007A/max17008 3) group the gate-drive components (bst capacitors, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 2. this diagram can be viewed as having four separate ground planes: i/o ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; the masters analog ground plane where sensitive analog components, the masters gnd pin, and v cc bypass capacitor go; and the slaves analog ground plane where the slaves gnd pin and v cc bypass capacitor go. the masters gnd plane must meet the pgnd plane only at a single point directly beneath the ic. similarly, the slaves gnd plane must meet the pgnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high-power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v out and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the load as is practical. see figure 15. dual and combinable qpwm graphics core controllers for notebook computers 34 ______________________________________________________________________________________ output 1 smps1 c out1 c out1 c out2 c out2 c in1 c in2 smps2 output 2 kelvin sense vias under the inductor (see MAX17007A evaluation kit) via to power ground v cc bypass capacitor ref bypass capacitor x-ray view. ic mounted on bottom side of pcb. ic layout connect gnd and pgnd the controller at one point only as shown connect the exposed pad to analog gnd via to analog ground power stage layout (top side of pcb) inductor l1 inductor l2 input power ground + inductor dcr sensing kelvin sense vias to inductor pad csl csh figure 15. pcb layout example
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers ______________________________________________________________________________________ 35 package type package code document no. 28 tqfn t2844-1 21-0139 chip information transistor count: 13,103 process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
MAX17007A/max17008 dual and combinable qpwm graphics core controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/08 initial release 1 9/08 changed max17007 to MAX17007A, changed ec table, and corrected typos 1C8, 11, 12, 13, 16, 18, 24, 25 2 10/08 released the max17008. updated the ec table. 1, 3, 6

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